TMS320VC5502 datasheet(11/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

3-77

Interrupt Table

................................................................................................................... 120

5-1

Recommended Crystal Parameters

........................................................................................... 131

5-2

CLKIN in Bypass Mode Timing Requirements

............................................................................... 133

5-3

CLKOUT in Bypass Mode Switching Characteristics

....................................................................... 133

5-4

CLKIN in Lock Mode Timing Requirements

.................................................................................. 134

5-5

CLKOUT in Lock Mode Switching Characteristics

.......................................................................... 134

5-6

EMIF Timing Requirements for ECLKIN

...................................................................................... 135

5-7

EMIF Switching Characteristics for ECLKOUT1

............................................................................. 135

5-8

EMIF Switching Characteristics for ECLKOUT2

............................................................................. 136

5-9

Asynchronous Memory Cycle Timing Requirements for ECLKIN

......................................................... 137

5-10

Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1

................................................ 137

5-11

Programmable Synchronous Interface Timing Requirements

............................................................. 140

5-12

Programmable Synchronous Interface Switching Characteristics

......................................................... 140

5-13

Synchronous DRAM Cycle Timing Requirements

........................................................................... 143

5-14

Synchronous DRAM Cycle Switching Characteristics

...................................................................... 143

5-15

EMIF.HOLD/HOLDA Timing Requirements

.................................................................................. 148

5-16

EMIF.HOLD/HOLDA Switching Characteristics

............................................................................. 148

5-17

Reset Timing Requirements

.................................................................................................... 149

5-18

Reset Switching Characteristics

............................................................................................... 149

5-19

External Interrupt and Interrupt Acknowledge Timing Requirements

..................................................... 151

5-20

External Interrupt and Interrupt Acknowledge Switching Characteristics

................................................ 151

5-21

XF Switching Characteristics

................................................................................................... 152

5-22

GPIO Pins Configured as Inputs Timing Requirements

.................................................................... 153

5-23

GPIO Pins Configured as Outputs Switching Characteristics

............................................................. 153

5-24

PGPIO Pins Configured as Inputs Timing Requirements

.................................................................. 154

5-25

PGPIO Pins Configured as Outputs Switching Characteristics

............................................................ 154

5-26

TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements

..................................... 155

5-27

TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics

.............................. 155

5-28

TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements

....................................................... 156

5-29

TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics

................................................... 156

5-30

TIM0/TIM1/WDTOUT Interrupt Timing Requirements

...................................................................... 158

5-31

McBSP Transmit and Receive Timing Requirements

...................................................................... 159

5-32

McBSP Transmit and Receive Switching Characteristics

.................................................................. 160

5-33

McBSP General-Purpose I/O Timing Requirements

........................................................................ 162

5-34

McBSP General-Purpose I/O Switching Characteristics

................................................................... 162

5-35

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)

................................. 163

5-36

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)

............................. 163

5-37

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)

................................. 165

5-38

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)

............................. 165

5-39

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)

................................. 166

5-40

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)

............................. 166

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