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DIO6971TST6 Datasheet(PDF) 8 Page - DIOO MICROCIRCUITS CO., LTD

Part # DIO6971TST6
Description  High-Efficiency 3A, 24V Input Synchronous Step Down Converter
PDF  10 Pages
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Manufacturer  DIOO [DIOO MICROCIRCUITS CO., LTD]
Direct Link  https://www.dioo.com/#/
Logo DIOO - DIOO MICROCIRCUITS CO., LTD

DIO6971TST6 Datasheet(HTML) 8 Page - DIOO MICROCIRCUITS CO., LTD

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DIO6971
www.dioo.com
© 2018 DIOO MICROCIRCUITS CO., LTD
DIO6971• V1.1
 
Output inductor L:
There are several considerations in choosing this inductor.
1) Choose the inductance to provide the desired ripple current. It is suggested to choose the ripple current to
be about 40% of the maximum output current. The inductance is calculated as:
L
=
%
40
)
/
1
(
,
,
MAX
OUT
SW
MAX
IN
OUT
OUT
I
F
V
V
V
where Fsw is the switching frequency and IOUT,MAX is the maximum load current. The DIO6971 regulator IC is
quite tolerant of different ripple current amplitude. Consequently, the final choice of inductance can be
slightly off the calculation value without significantly impacting the performance.
2) The saturation current rating of the inductor must be selected to be greater than the peak inductor current
under full load conditions.
ISAT,MIN>IOUT,MAX
+
L
F
V
V
V
SW
MAX
IN
OUT
OUT
2
)
/
1
(
,
3) The DCR of the inductor and the core loss at the switching frequency must be low enough to achieve the
desired efficiency requirement. It is desirable to choose an inductor with DCR<50mΩ to achieve a good
overall efficiency.
DIO6971 Recommended Table:
Layout Design:
The layout design of DIO6971 regulator is relatively simple. For the best efficiency and minimum noise
problems, we should place the following components close to the IC: CIN, L, R1 and R2.
1) It is desirable to maximize the PCB copper area connecting to GND pin to achieve the best thermal and
noise performance. If the board space allowed, a ground plane is highly desirable.
2) CIN must be close to Pins IN and GND. The loop area formed by CIN and GND must be minimized.
3) The PCB copper area associated with SW pin must be minimized to avoid the potential noise problem.
4) The components R1 and R2, and the trace connecting to the FB pin must NOT be adjacent to the SW net on
the PCB layout to avoid the noise problem.
5) If the system chip interfacing with the EN pin has a high impedance state at shutdown mode and the IN pin
is connected directly to a power source such as a Li-Ion battery, it is desirable to add a pull down 1MΩ
resistor between the EN and GND pins to prevent the noise from falsely turning on the regulator at shutdown
mode.
VOUT(V)
R1(kΩ)
R2(kΩ)
C2(pF)
L1/ Partnumber
1
10
40
Null
2.2μH/ SWPA6045S2R2NT (VLP6045-2R2M)
1.2
20.5
41.2
Null
2.2μH/ SWPA6045S2R2NT (VLP6045-2R2M)
1.8
40.2
32.4
Null
3.3μH/ SWPA8040S3R3NT (VLP6045-3R3M)
2.5
40.2
19.1
Null
3.3μH/ SWPA8040S3R3NT (VLP6045-3R3M)
3.3
40.2
13
22 (option)
4.7μH/ SWPA8040S4R7NT (CDRH8D43-4R7)
5
40.2
7.68
22 (option)
6.8μH/ SWPA8040S6R8MT (CDRH8D43-6R8)



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