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F24 Datasheet(PDF) 3 Page - Renesas Technology Corp |
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F24 Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 210 page ![]() RL78/F23, F24 1. OVERVIEW R01DS0446EJ0120 Rev.1.20 Page 3 of 207 Dec 31, 2025 1.3 Function Overview 1.3.1 RL78/F24 Functions List Table 1-4. RL78/F24 Functions List (1/2) Function Items Series Name R7F124FPJ R7F124FMJ R7F124FLJ R7F124FGJ R7F124FBJ Pin Count 100 pins 80 pins 64 pins 48 pins 32 pins Code flash 256 KB Data flash 16 KB RAM 24 KB Supply voltage range 2.7 V to 5.5 V Maximum operation frequency 40 MHz System clock Main system clock oscillator Crystal / ceramic / square wave 2 to 20 MHz (operating at 2.7 V to 5.5 V) High-speed on-chip oscillator Normal high accuracy 40 MHz (typ.) Low-speed on-chip oscillator For low-speed operation 15 kHz (typ.) Subsystem clock oscillator 32.768 kHz Note 6 None PLL Yes Clock for peripherals Low-speed on-chip oscillator For peripherals other than WDT 15 kHz (typ.) For WDT 15 kHz (typ.) POR When power supply is rising 1.56 V (typ.) When power supply is falling 1.55 V (typ.) LVD VDD voltage detection When power supply is rising 2.81 V (typ.) to 4.74 V (typ.) (in 6 steps) When power supply is falling 2.75 V (typ.) to 4.64 V (typ.) (in 6 steps) Functional safety Note 7 WWDT (window watchdog timer) Yes Flash memory fast CRC operation function Yes General purpose CRC operation Yes Flash memory ECC function Yes RAM 1-bit error correction function Yes RAM 2-bit error detection function Yes RS-CANFD lite RAM 1-bit error correction function Yes RS-CANFD lite RAM 2-bit error detection function Yes Invalid memory access detection function Yes Frequency detection function Yes Clock monitor function Yes Stack pointer monitor function Yes A/D test function Yes I/O ports Input/Output CMOS 86 ch 68 ch 52 ch 38 ch 25 ch Output CMOS 1 ch None Input Shared with oscillator pins 4 ch Note 6 2 ch Input only 1ch Power supply pins For internal circuits VDD, VSS, REGC For I/O ports EVDD0, EVSS0 EVDD1, EVSS1 EVDD0, EVSS0 None For analog circuits (AD, DA, COMP) VDD, VSS (AVREFP, AVREFM for AD) Multiply/divide and multiply- accumulate functions Multiply 16 bits × 16 bits (signed) 16 bits × 16 bits (unsigned) Divide 32 bits ÷ 32 bits (unsigned) Multiply-accumulate 16 bits × 16 bits + 32 bits (signed) 16 bits × 16 bits + 32 bits (unsigned) Arithmetic instructions (extended instruction set) Yes Vectored interrupt sources External 16 ch Notes 4, 5 16 ch Notes 4, 5 15 ch Notes 3, 5 14 ch Note 2 10 ch Note 1 Internal 53 ch Note 4 53 ch Note 4 53 ch Note 3 53 ch Note 2 53 ch Note 1 Key return detection 8 ch 6 ch DTC 44 sources 43 sources Timer TAU 16 bits (8 ch × 2) RTC 1 ch Timer RJ 16 bits × 1 Timer RDe 16 bits × 2 (with PWMOPA and dithering / gate function) (Notes are listed on the next page.) |
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