F24 datasheet(71/210 Pages) RENESAS

71 / 210 page

RL78/F23, F24

3. ELECTRICAL SPECIFICATIONS (GRADE 3)

R01DS0446EJ0120 Rev.1.20

Page 71 of 207

Dec 31, 2025

(6)

During communication at same potential (simplified I2C mode)

(SDAr: N-ch open-drain output (EVDD tolerance) mode, SCLr: normal output mode)

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCLr clock frequency

fSCL

1000 Note

kHz

Hold time when SCLr = “L”

tLOW

475

Hold time when SCLr = “H”

tHIGH

475

Data setup time (reception)

tSU:DAT

1/fMCK + 85

Data hold time (transmission)

tHD:DAT

Cb = 50 pF, Rb = 2.7 k

305

Note fCLK

≤ fMCK/4 must also be satisfied.

Simplified I2C mode connection diagram (during communication at same potential)

Simplified I2C mode serial transfer timing (during communication at same potential)

Caution Select the normal input buffer and N-ch open-drain output mode for the SDAr pin and normal output

mode for the SCLr pin.

Remarks 1. Rb [Ω]: Communication line (SDAr) pull-up resistance, Cb [F]: Communication line (SCLr, SDAr) load

capacitance

2. r: IICr (r = 00, 01, 10, 11)

3. fMCK: Serial array unit operation clock frequency

User's device

RL78

microcontroller

SDAr

SCLr

SDA

SCL

VDD

1/fSCL

tLOW

tHIGH

SCLr

SDAr

tHD:DAT

tSU:DAT

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