F24 datasheet(83/210 Pages) RENESAS

83 / 210 page

RL78/F23, F24

3. ELECTRICAL SPECIFICATIONS (GRADE 3)

R01DS0446EJ0120 Rev.1.20

Page 83 of 207

Dec 31, 2025

3.5.3 On-chip Debug (UART)

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Transfer rate

–

115.2 k

1 M

bps

3.5.4 LIN/UART Module (RLIN3) UART Mode

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Transfer rate

–

Operation mode,

HALT mode

LIN communication clock source (fCLK or fMX):

4 to 40 MHz

4000

kbps

SNOOZE mode

LIN communication clock source (fCLK):

2 to 40 MHz

9.6

3.5.5 CAN-FD Communication Interface (RS-CANFD lite) Timing

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Transfer rate

–

Classical CAN mode

Mbps

CAN-FD mode

Data bit rate

Mbps

CAN-FD mode

Nominal bit rate

Mbps

Internal delay time Note

tNODE

Note tNODE = Internal input delay time (tINPUT) + Internal output delay time (tOUTPUT)

Image of Internal delay

RL78/F24

CAN controller

CTXD0

CRXD0

Internal output delay time

（

tOUTPUT）

Internal input delay time

（

tINPUT）

F24 Datasheet(PDF) 83 Page - Renesas Technology Corp

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