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TAS2020 Datasheet(PDF) 61 Page - Texas Instruments |
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TAS2020 Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 79 page ![]() 7.6 PAGE 6 Registers Table 7-82 lists the memory-mapped registers for the PAGE 6 registers. All register offset addresses not listed in Table 7-82 should be considered as reserved locations and the register contents should not be modified. Table 7-82. PAGE 6 Registers Address Acronym Description Section 0h PAGE Device Page Section 7.6.1 34h DEV_PERF_TUNING_24 Device performance tuning Section 7.6.2 38h DEV_PERF_TUNING_18 Device performance tuning Section 7.6.3 48h DEV_PERF_TUNING_25 Device performance tuning Section 7.6.4 7.6.1 PAGE Register (Address = 0h) [Reset = 00h] Return to the Summary Table. The devices memory map is divided into pages and books. This register sets the page. Table 7-83. PAGE Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255 7.6.2 DEV_PERF_TUNING_24 Register (Address = 34h) [Reset = 400000h] Return to the Summary Table. Device performance tuning Table 7-84. DEV_PERF_TUNING_24 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_24[ 23:0] R/W 400000h Addresses 0x34 to 0x36 are combined. Can be configured using the PPC3 Software. 7.6.3 DEV_PERF_TUNING_18 Register (Address = 38h) [Reset = 400000h] Return to the Summary Table. Device performance tuning Table 7-85. DEV_PERF_TUNING_18 Register Field Descriptions Bit Field Type Reset Description 23-0 DEV_PERF_TUNING_18[ 23:0] R/W 400000h Addresses 0x38 to 0x3A are combined. Can be configured using the PPC3 Software. 7.6.4 DEV_PERF_TUNING_25 Register (Address = 48h) [Reset = 166666h] Return to the Summary Table. Device performance tuning www.ti.com TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: TAS2020 |
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