RZSLASHG2N datasheet(106/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 3. Electrical Characteristics

R01DS0483EJ0101 Rev.1.01

Page 106 of 169

Jun 30, 2025

Table 3.16.3 Ethernet Control Timing (RGMII Tx clock internal Delay Mode) [RZ/G2H, RZ/G2M V1.3,

RZ/G2M V3.0, RZ/G2N]

Conditions: VDDQ33 = 3.3 ± 0.2 V, VDDQ25_ETH = 2.5 ± 0.1V [RZ/G2H, RZ/G2M V1.3, RZ/G2M V3.0, RZ/G2N],

Tc = -40 to +115 °C [RZ/G2H, RZ/G2M V1.3],

Ta = -40 to +85 °C [RZ/G2M V3.0, RZ/G2N],

Tj = -40 to +115 °C [RZ/G2M V3.0, RZ/G2N], GND = VSS = 0 V, CL = 30 pF

Recommend: Connection of series 25 Ω as damping resistor to RGMII output buffer. [RZ/G2H, RZ/G2M V1.3,

RZ/G2M V3.0, RZ/G2N]

Item

Symbol

Min.

Typ.

Max.

Unit

Figures

AVB_TXCREFCLK cycle time

—

125 – 50 ppm

—

125 + 50 ppm MHz

—

AVB_TXC cycle time *1

Tcyc

7.2

8.8

AVB_TXC duty cycle (in 1 Gbps)

Duty_G

AVB_TXC duty cycle (in 100 Mbps)

Duty_T

AVB_TX_CTL setup time

TsetupT

1.2 *2

2.0

—

Figure 3.16.5

0.95 *3

AVB_TX_CTL hold time

TholdT

1.2

2.0

—

AVB_TD[3:0] setup time

TsetupT

1.2 *2

2.0

—

0.95 *3

AVB_TD[3:0] hold time

TholdT

1.2

2.0

—

Notes: 1. For 100 Mbps, Tcyc will scale to 40 ns ± 4 ns respectively.

2. For [RZ/G2H, RZ/G2M V3.0, RZ/G2N].

3. For [RZ/G2M V1.3].

Figure 3.16.5 RGMII Delay Mode Transmission Timing

AVB_TXC

AVB_TD[3:0]

AVB_TX_CTL

TD[3:0]

TD[7:4]

TD[3:0]

TXEN

TXERR

TsetupT

TXC with internal

delay added

TholdT

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