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RZ/G2N Datasheet(PDF) 105 Page - Renesas Technology Corp |
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RZ/G2N Datasheet(HTML) 105 Page - Renesas Technology Corp |
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105 / 169 page ![]() RZ/G Series, 2nd Generation Datasheet Section 3. Electrical Characteristics R01DS0483EJ0101 Rev.1.01 Page 105 of 169 Jun 30, 2025 Table 3.16.2 Ethernet Control Timing (RGMII 1Gbps Mode) Conditions: VDDQ33 = 3.3 ± 0.2 V, VDDQ25_ETH = 2.5 ± 0.1V [RZ/G2H, RZ/G2M V1.3, RZ/G2M V3.0, RZ/G2N], VDDQ25_AVB0 = 2.5 ± 0.2V [RZ/G2E], Tc = -40 to +115 °C [RZ/G2H, RZ/G2M V1.3], Ta = -40 to +85 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E], Tj = -40 to +115 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E], GND = VSS = 0 V, CL = 30 pF Recommend: Connection of series 25 Ω as damping resistor to RGMII output buffer. [RZ/G2H, RZ/G2M V1.3, RZ/G2M V3.0, RZ/G2N] Item Symbol Min. Typ. Max. Unit Figures AVB_TXCREFCLK cycle time — 125 – 50 ppm — 125 + 50 ppm MHz — AVB_TXC cycle time Tcyc 7.2 8 8.8 ns AVB_TXC duty cycle Duty_G 45 50 55 % AVB_TX_CTL to clock output skew TskewT -500 0 500 ps Figure 3.16.3 AVB_TD[3:0] to clock output skew TskewT -500 0 500 ps AVB_RXC cycle time Tcyc 7.2 8 8.8 ns — AVB_RXC duty cycle Duty_G 45 50 55 % AVB_RX_CTL to clock input skew TskewR 1 1.8 2.6 ns Figure 3.16.4 AVB_RD[3:0] to clock input skew TskewR 1 1.8 2.6 ns Figure 3.16.3 RGMII 1 Gbps Mode Transmission Timing Figure 3.16.4 RGMII 1 Gbps Mode Reception Timing AVB_TXC AVB_TD[3:0] AVB_TX_CTL TD[3:0] TD[7:4] TXEN TXERR TskewT AVB_RXC AVB_RD[3:0] AVB_RX_CTL RD[3:0] RD[7:4] RXDV RXERR TskewR |
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