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RZ/A1M Datasheet(PDF) 71 Page - Renesas Technology Corp |
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RZ/A1M Datasheet(HTML) 71 Page - Renesas Technology Corp |
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71 / 137 page ![]() R01DS0479EJ0100 Rev.1.00 Page 71 of 137 Dec. 25, 2024 RZ/A1H Group, RZ/A1M Group 3. Electrical Characteristics Figure 3.14 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control)) Read Note: * The waveform for DACKn and TENDn is when active low is specified. Write Th t AD1 tRSD t RSD t RDS1 t CSD1 t RWD1 T1 Twx T2 Tf t WDD1 t BSD t WDH1 t RDH1 t AD1 t CSD1 CKIO A25 to A0 CSn WEn RD D31 to D0 D31 to D0 RD/ WR RD/ WR BS WAIT DACKn TENDn* t DACD t DACD t BSD t WTS tWTS t RWD1 tRWD1 t RWD1 t WED1 t WED1 t WTH t WTH |
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