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RZ/N2L Datasheet(PDF) 50 Page - Renesas Technology Corp |
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RZ/N2L Datasheet(HTML) 50 Page - Renesas Technology Corp |
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50 / 128 page  CKIO tDACD tDACD DACK*1 T1 T2 A25 to A0 tAD1 tAD1 tCSD1 tAS tRWD1 CS5#, CS3#, CS2#, CS0# RD/WR# tRSD RD# tRSD tRWD1 tCS D15 to D0 tRDS1 tRDH1 tAH tWED1 tAH tWED1 WE1#, WE0# tWDD1 tWDH1 tWDH4 D15 to D0 BS# tBSD tBSD Read Write Tw tWTS tWTH WAIT# Taw T1 T2 Tw Taw tAD1 tAD1 tCSD1 tCSD1 tCSD1 tRWD1 tRWD1 tCS tAS tRSD tAH tRSD tRDS1 tRDH1 tWED1 tWED1 tAH tWDH1 tWDH4 tWDD1 tBSD tBSD tDACD tDACD tWTS tWTH Note 1. DACK is waveform when active-low is specified. Figure 2.14 SRAM interface basic bus cycle (software wait 1, external wait enabled (WM = 0), no idle cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0140 Rev.1.40 Mar 31, 2026 Page 50 of 128 |
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