RZSLASHN2L datasheet(15/128 Pages) RENESAS

15 / 128 page

Table 1.18

Pin functions (2 of 7)

Classification

Pin name

I/O

Description

Debugging interface

TRST#

Input

Test reset pin for the on-chip emulator

TMS

I/O

Test mode select pin for the on-chip emulator

Functions as the SWDIO pin in serial wire debug

(SWD) mode

TDI

Input

Test data input pin for the on-chip emulator

TDO

Output

Test data output pin for the on-chip emulator

TCK

Input

Test clock pin for the on-chip emulator

Functions as the SWCLK pin in serial wire debug

(SWD) mode

TRACECLK

Output

Outputs the clock for synchronization with trace data

TRACECTL

Output

Outputs the enable signal for trace control

TRACEDATA0 to TRACEDATA7

Output

Output trace data

Bus state controller (BSC)

A25 to A0

Output

Output the address

D15 to D0

I/O

Input and output the data

CS0#, CS2#, CS3#, CS5#

Output

Output the chip select signal for the external memory

or device.

RD#

Output

Outputs the strobe signal which indicates a read is in

progress.

RD/WR#

Output

Outputs the strobe signal which indicates a read or

write access

BS#

Output

Outputs the status signal which indicates the start of

the bus cycle

AH#

Output

Outputs the address hold signal for the device that

uses the multiplexed I/O interface

WAIT#

Input

Inputs the external wait control signal which inserts a

wait cycle into the bus cycle

WE0#

Output

Outputs the write strobe signal to D7 to D0

WE1#

Output

Outputs the write strobe signal to D15 to D8

DQMLL

Output

Outputs the data mask enable signal to D7 to D0 when

SDRAM is connected

DQMLU

Output

Outputs the data mask enable signal to D15 to D8

when SDRAM is connected

RAS#

Output

Outputs the row-address strobe signal to the SDRAM.

This pin should be connected to the RAS# pin on the

SDRAM.

CAS#

Output

Outputs the column-address strobe signal to the

SDRAM. This pin should be connected to the CAS#

pin on the SDRAM.

CKE

Output

Outputs the clock enable signal to the SDRAM. This

pin should be connected to the CKE pin on the

SDRAM.

Direct memory access

controller (DMAC)

DREQ

Input

Inputs the DMA transfer request signal from the

external device

DACK

Output

Outputs the acknowledge signal which indicates

acceptance of the DMA transfer request from the

external device

TEND

Output

Outputs the DMA transfer end signal

Interrupt

NMI

Input

Inputs the non-maskable interrupt request signal

IRQ0 to IRQ15

Input

Input the external interrupt request signal

RZ/N2L Datasheet

1. Overview

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

Page 15 of 128

RZ/N2L Datasheet(PDF) 15 Page - Renesas Technology Corp

RZ/N2L Datasheet(HTML) 15 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL