RZSLASHN2L datasheet(90/128 Pages) RENESAS

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Table 2.36

xSPI timing

Parameter

Symbol

1.8 V

3.3 V

Unit

Reference

figure

Min.

Max.

Min.

Max.

Cycle time

SDR

tPERIOD

7.5

—

13.3

—

Figure 2.73

DDR

10.0

—

13.3

—

Clock output slew rate

tSRck

0.75/0.56*2

—

0.56

—

V/ns

Clock duty cycle distortion

tCKDCD

0.0

tPERIOD ×

0.05

0.0

tPERIOD

× 0.05

Clock minimum pulse width

tCKMPW

tPERIOD ×

0.45

—

tPERIOD ×

0.45

—

Differential clock crossing voltage

VOX(AC) 0.4 × VCC18 0.6 × VCC18 —

—

DS duty cycle distortion

tDSDCD

0.0

tPERIOD ×

0.04

0.0

tPERIOD

× 0.04

DS minimum pulse width

tDSMPW

tPERIOD ×

0.41

—

tPERIOD ×

0.41

—

Data input/output slew rate

tSR

0.75/0.56*2

—

0.56

—

V/ns

Data input setup time (to CK)

SDR

tSU

2.0

—

2.4

—

Figure 2.74

Data input hold time (to CK)

1.0

—

1.0

—

Data output delay time

tOD

—

1.0*3

—

1.4*3

Data output hold time

tOH

-1.0

—

-2.3

—

Data output buffer off time

tBOFF

-1.0

—

-2.3

—

Data input setup time (to DS)

DDR*1

tSU

-0.8

—

-0.8

—

Figure 2.75,

Figure 2.76

Data input hold time (to DS)

tPERIOD ×

0.41 - 0.8

—

tPERIOD ×

0.41 - 0.8

—

Data output setup time (to CK)

tSUO

1.0

—

1.0

—

Data output hold time (to CK)

tHO

1.0

—

1.0

—

CS low to clock high

tCSLCKH 6.0/8.0*2 *4

—

8.0*4

—

Figure 2.74

to Figure

2.76

Clock low to CS high

tCKLCSH 6.0/8.0*2

—

8.0

—

CS high time

tCSTD

tPERIOD

DS low to CS high

tDSLCSH 6.0/8.0*2 *5

—

10.6*5

—

Figure 2.77

CS high to DS tri-state

tCSHDST 0.0

tPERIOD

0.0

tPERIOD

CS low to DS low *8

tCSLDSL

0.0

16.0 *9

0.0

20.0 *9

DS tri-state to CS low

tDSTCSL 0.0

—

0.0

—

CK low to DS low *6

tCKLDSL

—

(0.45 + e) ×

tPERIOD - 2 *7

—

(0.45 +

e) ×

tPERIOD

- 2 *7

Note 1. The DS shift setting (WRAPCFG.DSSFTCSx[4:0]) is 01000b for xSPI200.

Note 2. Specification at 133 MHz / Specification at 100 MHz

Note 3. These are values when the OEN assertion is extended in the Output Enable Asserting extension bit (COMCFG.OEASTEX = 1).

Note 4. These are the values when the CS assertion is extended in the CS asserting extension bit (LIOCFGCSn.CSASTEX = 1).

Note 5. These are the values when the tCKLDSL constraint is satisfied.

Note 6. This constraint is necessary only to satisfy the tDSLCSH requirement in JESD251, which specifies that tDSLCSH must be at least 80%

of tPERIOD. Set LIOCFGCSn.CSNEGEX to the appropriate value to ensure the memory specification complies with this constraint.

Note 7. e = LIOCFGCSn.CSNEGEX

Note 8. If the DS is high during the command and modifier phase when using JESD251 Profile 2.0 memory, the time from CS low to DS

high must also meet this specification.

Note 9. When using JESD251 Profile 1.0 memory or JESD251 Profile 2.0 memory with LIOCFGCSn.LATEMD set to 0, this constraint does

not apply if the internal pull-down resistor of the DS pin is enabled.

RZ/N2L Datasheet

2. Electrical Characteristics

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

Page 90 of 128

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