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RZ/N2L Datasheet(PDF) 107 Page - Renesas Technology Corp

Part # RZ/N2L
Description  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  128 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RZ/N2L Datasheet(HTML) 107 Page - Renesas Technology Corp

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(2) Asynchronous SRAM Interface Mode
Table 2.43
PHOSTIF timing (Asynchronous SRAM interface mode)
No.
Parameter
Symbol
Min.
Max.
Unit
Reference
figure
1
Address, HCS0#/HCS1# input setup time (to HWRSTB#, HWR0#/
HWR1# ↓)
tADDWRS
0
―
ns
Figure 2.95 to
Figure 2.98
2
HWR0#/HWR1# and HWRSTB# recovery time (High-level width)
tWRW
20.0
―
ns
3
Data input setup time (to HWRSTB#, HWR0#/HWR1# ↓)
tWRS
0
―
ns
4
Data input hold time (to HWRSTB#, HWR0#/HWR1# ↑)
tWRH
0
―
ns
5
HWAIT# output delay time (to HCS0#/HCS1# ↓)
tCLZ
1.0
―
ns
6
HWAIT# output delay time (to HWRSTB#, HWR0#/HWR1# ↓)
tWAITD
1.0
―
ns
7
HWAIT# valid data output delay time (for HWRSTB#, HWR0#/HWR1#
↓)
tWRWAITF
―
39.2
ns
8
HWAIT# valid data output hold time (for HWRSTB#, HWR0#/HWR1# ↑) tWAITVH
0
―
ns
9
HWAIT# output hold time (to HWR0#/HWR1#, HWRSTB# ↑)
tWAITH
―
11.0
ns
10
HWAIT# output hold time (to HCS0#/HCS1# ↑)
tCHZ
―
11.0
ns
11
Address and HCS0#/HCS1# input setup time (to HRD# ↓)
tADDRDS
0
―
ns
12
Address input hold time in page access (to HRD# ↑)
tADDRDH
0
―
ns
13
HRD# recovery time (High-level width)
tRDW
20.0
―
ns
14
Data and HWAIT# output delay time (to HRD# ↓)
tRDLZ
1.0
―
ns
15
HWAIT# valid data output delay time (to HRD# ↓)
tRDWAITF
―
39.2
ns
16
Data fixing time (to HWAIT# ↑)
tWAITR
0
―
ns
17
Data and HWAIT# valid data output hold time (to HRD# ↑)
tDATAOH
1.0
―
ns
18
Data and HWAIT# output hold time (to HRD# ↑)
tRDHZ
―
11.0
ns
19
Data and HWAIT# output delay time in on-page access (to addresses)
tPAGEOND
18.0
29.2
ns
20
Data and HWAIT# output delay time in off-page access (to addresses)
(when not crossing a 16-byte boundary)
tPAGEOFD
18.0
29.2
ns
20
Data and HWAIT# output delay time in off-page access (to addresses)
(when crossing a 16-byte boundary)
tPAGEOFD
18.0
29.2
ns
21
HWAIT# valid data output delay time (to HCS0#/HCS1# ↓)
tWAITVD
―
39.2
ns
22
Data fixing time (to addresses)
tADDFIX
18.0
―
ns
RZ/N2L Datasheet
2. Electrical Characteristics
R01DS0397EJ0140 Rev.1.40
Mar 31, 2026
Page 107 of 128



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