RZSLASHN2L datasheet(121/128 Pages) RENESAS

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Table 2.51

Debug interface timing (2 of 2)

Parameter

Symbol

Min.

Max.

Unit

Reference

figure

Capture register setup time

tCAPTS

—

Figure 2.112

Capture register hold time

tCAPTH

—

Update register delay time

tUPDATED

—

Trace clock cycle

tTCYC

—

Figure 2.113

Output load:

15 pF

Trace data delay

time

Trace clock: P18_6

tTDT

-2.9

3.2

Trace clock: P17_4

-2.8

3.3

Trace clock: P22_2

-2.2*2

4.0

Note 1. This value is the minimum cycle time for the normal operation of internal circuits.

The actual cycle time should be determined in consideration of the TCK capture edge timing and cable length of the connected ICE.

Note 2. If P22_1 is not used as trace control, this value is -1.8 ns.

tTCKcyc

tTCKH

tTCKL

TCK

VIH

VIL

1/2 VCC33

VIH

Figure 2.110

TCK input timing

tSWDO

tTDOD

SWDIO (output)

TDO

tTMSS

tTMSH

TMS/SWDIO (input)

tTDIS

tTDIH

TDI

tTCKcyc

TCK

Figure 2.111

Data transfer timing

RZ/N2L Datasheet

2. Electrical Characteristics

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

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