MK68564 datasheet(34/46 Pages) STMICROELECTRONICS

34 / 46 page

SDLC.

D6 : CRC/Framing Error

In Asynchronous modes, if a Framing Error occurs,

this bit is set to a one for the receive character in

which the framing error occurred. When this bit is set

to a one, a Special Receive Condition interrupt will

be requested, if receiver interrupts are enabled.

Detection of a Framing Error adds an additional one-

half bit time to the character time, so that the Fra-

ming Error is not interpreted as a new start bit.

In Synchronous and SDLC modes, this bit indicates

the result of comparing the received CRC value to

the appropriate check value. A zero indicates that a

match has occurred. This bit is usually set since

most bit combinations result in a non-zero CRC, ex-

cept for a correctly completed message. Receiver

interrupts are not requested by the CRC Error bit.

The CRC/Framing bit is not latched in any receiver

mode. It is always updated when the next character

is received. An Error Reset command (command 6)

will always reset this bit to zero.

D5 : Receive Overrun Error

This bit indicates that the receive data FIFO has o-

verflowed. Only the character that has been written

over is flagged with this error. When the character

is read, the error condition is latched until reset by

the Error Reset command (command 6). If receiver

interrupts are enabled, the overrun character and all

subsequent characters received, until the Error Re-

set command is issued, will generate a Special Re-

ceive Condition interrupt request.

D4 : Parity Error

When parity is enabled, this bit is set to a one for

those characters whose parity does not match the

programmed sense (even/odd). This bit is latched

so that once an error occurs, it remains set until the

Error Reset command (command 6) is issued. If pa-

rity is a Special Receive Condition, a Parity is a Spe-

cial Receive Condition, a Parity Error will cause a

Special Receive Condition interrupt request on the

character containing the error and on all subsequent

characters until the Error Reset command is issued.

D3, D2, D1 : Residue Codes 2, 1, and 0

In those cases of the SDLC receive mode, where the

I-field is not an integral multiple of the character

length, these three bits indicate the length of the re-

sidual I-field read in the previous bytes. These codes

are meaningful only for the transfer in which the End

Of Frame bit is set. This field is set to 000 by a chan-

nel or hardware reset and can leave this state only

if SDLC mode is selected, and a character is recei-

ved.

FOR EIGHT BITS PER CHARACTER

If a receive character length, different from eight bits,

is used for the I-field, a table similar to the previous

one may be constructed for each different character

length. For no residue (that is, the last character

boundary coincides with the boundary of the I-field

and CRC field), the Residue codes are as follows :

D0 : All Sent

This bit is only active in Asynchronous modes ; it is

always High in Synchronous or SDLC modes. This

bit is Low while the transmitter is sending characters :

it will go High only after all the bits of the character

are transmitted, and the transmit buffer is empty.

DATA REGI STER (DATARG)

The Data Register is actually two separate regis-

ters ; a write only register that is the Transmit Buffer,

and a read only register that is the Receiver Buffer.

The Receiver Buffer is also the top register of a three

Residue

Code 2

Residue

Code 1

Residue

Code 0

I-Field

Bits

Byte

I-Field

Bits

I n Second

Byte

Bits P er Character Residue

Code 2

Residue

Code 1

Residue

Code 0

8 Bits Per Character

7 Bits Per Character

6 Bits Per Character

5 Bits Per Character

D 5

DATA

I-F iel Bit s ar e Ri ght -justified in all Cases.

MK68564

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