TMS320VC5509 datasheet(67/124 Pages) TI

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Functional Overview

April 2001 − Revised January 2008

SPRS163H

The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in

Figure 3−18.

NOTE: It is possible to have active interrupts simultaneously from both the external interrupt 4

(INT4) and the real-time clock (RTC). When an interrupt is detected in this bit, the real-time

clock status register should be polled to determine if the real-time clock is the source of the

interrupt.

Reserved

RTOS

DLOG

BERR

R/W−00000†

R/W−0

I2C

TINT1

DMAC3

DMAC2

INT4/RTC

DMAC0

XINT0

INT1

R/W−0

LEGEND: R = Read, W = Write, n = value after reset

† Always write zeros.

Figure 3−18. IFR1 and IER1 Bit Locations

Table 3−39. IFR1 and IER1 Register Bit Fields

BIT

FUNCTION

NUMBER

NAME

FUNCTION

15−11

−

Reserved for future expansion. These bits should always be written with 0.

RTOS

Real-time operating system interrupt flag/mask bit

DLOG

Data log interrupt flag/mask bit

BERR

Bus error interrupt flag/mask bit

I2C

I2C interrupt flag/mask bit

TINT1

Timer 1 interrupt flag/mask bit

DMAC3

DMA channel 3 interrupt flag/mask bit

DMAC2

DMA channel 2 interrupt flag/mask bit

INT4/RTC

This bit can be used as either the external user interrupt 4 flag/mask bit, or the real-time clock

interrupt flag/mask bit.

DMAC0

DMA channel 0 interrupt flag/mask bit

XINT0

McBSP transmit 0 interrupt flag/mask bit

INT1

External user interrupt 1 flag/mask bit

3.10.2

Interrupt Timing

The external interrupts (INT[4:0]) are synchronized to the CPU by way of a two-flip-flop synchronizer. The

interrupt inputs are sampled on falling edges of the CPU clock. A sequence of 1-1-0-0-0 on consecutive cycles

on the interrupt pin is required for an interrupt to be detected. Therefore, the minimum low pulse duration on

the external interrupts on the 5509 is three CPU clock periods.

TMS320VC5509 Datasheet(PDF) 67 Page - Texas Instruments

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