TAS5705PAP datasheet(45/71 Pages) TI

45 / 71 page

TAS5705

www.ti.com ...................................................................................................................................................................................................... SLOS549 – JUNE 2008

10. This completes the initialization sequence. From this step on, no further constraints are imposed on PDN,

MUTE, and clocks.

11. During normal operation the user may do the following:

Write to the master or individual-channel volume registers.

Write to the soft-mute register.

Write to the clock and serial data interface format registers (in manual clock mode only).

Write to bit 6 of register 0x05 to enter/exit all-channel shutdown. No other bits of register 0x05 may be

altered. After issuing the all-channel shutdown command, no further I2C transactions that address this

device are allowed for a period of at least: 1 ms + 1.3 × (period specified in start/stop register 0x1A) .

PDN may be asserted (low) at any time. Once PDN is asserted, no I2C transactions that address this

device may be issued until PDN has been deasserted and the part has returned to active mode.

NOTE: When the device is in a powered down state (initiated via PDN), the part is not reset if RESET

is asserted.

NOTE: Once RESET is asserted, and as long as the part is in a reset state, the part does not power

down if PDN is asserted. For powering the part down, a negative edge on PDN must be issued when

RESET is high and the part is not in a reset state.

NOTE: No registers besides those explicitly listed in Steps a.–d. should be altered during normal

operation (i.e., after exiting all-channel shutdown).

NOTE: No registers should be read during normal operation (i.e., after exiting all-channel shutdown) .

12. To reconfigure registers:

Return to all-channel shutdown (observe the shutdown wait time as specified in Step 11.d.).

Drive PDN = 1, and hold MUTE stable.

Provide a stable MCLK, LRCLK, and SCLK.

Repeat configuration starting from step (6).

Table 7. Serial Control Interface Register Summary (1)

NO. OF

INITIALIZATION

SUBADDRESS

CONTENTS

BYTES

VALUE

A u indicates unused bits.

0x00

Clock control register