TAS5705PAP datasheet(23/71 Pages) TI

23 / 71 page

SSTIMER FUNCTIONALITY

CLOCK, AUTODETECTION, AND PLL

SERIAL DATA INTERFACE

PWM Section

TAS5705

www.ti.com ...................................................................................................................................................................................................... SLOS549 – JUNE 2008

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when

a transition occurs on the RESET pin. The capacitor on the SSTIMER pin is slowly charged through an internal

current source, and the charge time determines the rate at which the output transitions from a near zero duty

cycle to the duty cycle that is present on the inputs. This allows for a smooth transition with no audible pop or

click noises when the RESET pin transitions from high-to-low or low-to-high.

For a high-to-low transition of the RESET pin (shutdown case), it is important for the modulator to remain

switching for a period of at least 10 ms (if using a 2.2 nF capacitor). Larger capacitors will increase the

start-up/shutdown time, while capacitors smaller than 2.2 nF will decrease the start-up/shutdown time. The inputs

MUST remain switching on the shutdown transition to allow the outputs to slowly ramp down the duty cycle to

near zero before completely shutting off. The SSTIMER pin should be left floating for BD modulation and also for

SE (single-ended) mode.

The TAS5705 DAP is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the clock control register.

The TAS5705 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×

fS LRCLK. The timing relationship of these clocks to SDIN1/2 is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the internal clock.

The DAP can autodetect and set the internal clock-control logic to the appropriate settings for the frequencies of

32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or

192 kHz). The automatic sample-rate detection can be disabled and the values set via I2C in the clock control

The DAP also supports an AM interference-avoidance mode during which the clock rate is adjusted, in concert

with the PWM sample rate converter, to produce a PWM output at 7 × fS, 8 × fS, or 6 × fS.

The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.

Serial data is input on SDIN1/2. The PWM outputs are derived from SDIN1/2. The TAS5705 DAP accepts 32-,

44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in left-justified, right-justified,

and I2S serial data formats.

The TAS5705 DAP device uses noise-shaping and sophisticated error-correction algorithms to achieve high

power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper that

has >100-dB SNR performance from 20 Hz to 20 kHz. The PWM section accepts 24-bit PCM data from the DAP

and outputs four PWM audio output channels. The TAS5705 PWM SECTION supports bridge-tied loads.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual-channel de-emphasis filters for 32-, 44.1-, and 48-kHz are included and

can be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

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