JS48F4400PCZ00 datasheet(62/102 Pages) NUMONYX

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Numonyx™ Wireless Flash Memory (W18)

Datasheet

November 2007

Order Number: 290701-18

Numonyx™ Wireless Flash Memory (W18)

11.3.2

Setup

After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7]

transitions from a 1 to a 0 indicating that the WSM is busy with EFP algorithm startup.

A delay before checking SR[7] is required to allow the WSM time to perform all of its

setups and checks (VPP level and block lock status). If an error is detected, Status

Note:

After the EFP Setup and Confirm command sequence, reads from the device

automatically output Status Register data. Do not issue the Read Status Register

command; it will be interpreted as data to program at WA0.

11.3.3

Program

After setup completion, the host programming system must check SR[0] to determine

“data-stream ready" status (SR[0]=0). Each subsequent write after this is a program-

data write to the flash array. Each cell within the memory word to be programmed to 0

receives one WSM pulse; additional pulses, if required, occur in the verify phase.

SR[0]=1 indicates that the WSM is busy applying the program pulse.

The host programmer must poll the device's Status Register for the "program done"

state after each data-stream write. SR[0]=0 indicates that the appropriate cell(s)

within the accessed memory location have received their single WSM program pulse,

and that the device is now ready for the next word. Although the host may check full

status for errors at any time, it is only necessary on a block basis, after EFP exit.

Addresses must remain within the target block. Supplying an address outside the

target block immediately terminates the program phase; the WSM then enters the EFP

verify phase.

The address can either hold constant or it can increment. The device compares the

incoming address to that stored from the setup phase (WA0); if they match, the WSM

programs the new data word at the next sequential memory location. If they differ, the

WSM jumps to the new address location.

The program phase concludes when the host programming system writes to a different

block address, and data supplied must be FFFFh. Upon program phase completion, the

device enters the EFP verify phase.

11.3.4

Verify

A high percentage of the flash bits program on the first WSM pulse. However, for those

cells that do not completely program on their first attempt, EFP internal verification

identifies them and applies additional pulses as required.

The verify phase is identical in flow to the program phase, except that instead of

programming incoming data, the WSM compares the verify-stream data to that which

was previously programmed into the block. If the data compares correctly, the host

programmer proceeds to the next word. If not, the host waits while the WSM applies an

additional pulse(s).

The host programmer must reset its initial verify-word address to the same starting

location supplied during the program phase. It then reissues each data word in the

same order as during the program phase. Like programming, the host may write each

subsequent data word to WA0 or it may increment up through the block addresses.

The verification phase concludes when the interfacing programmer writes to a different

block address; data supplied must be FFFFh. Upon completion of the verify phase, the

device enters the EFP exit phase.

JS48F4400PCZ00 Datasheet(PDF) 62 Page - Numonyx B.V

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