6V7 datasheet(5/298 Pages) RENESAS

5 / 298 page

Rev.1.00

May 18, 2004

page 5 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

Item

Performance

Number of basic instructions

91 instructions

Shortest instruction execution time

62.5 ns(f(XIN)=16 MHz)

Memory

ROM

Refer to Figure 1.5.1 ROM development

size

RAM

10K bytes to 16K bytes

OSD ROM

60K bytes

OSD RAM

2.2K bytes

I/O port

P0 to P10

8 bits ✕ 7, 6 bits ✕ 1, 5 bits ✕ 2, 4 bits ✕ 1

Multifunction

TA0, TA1, TA2, TA3, TA4

16 bits ✕ 5

timer

TB0, TB1, TB2

16 bits ✕ 3

Serial I/O

UART0

1 unit: UART or clock synchronous

UART2

1 unit: UART or clock synchronous

Multi-master I2C-BUS interface 0 1 unit (2 channels)

Multi-master I2C-BUS interface 1 1 unit (1 channel)

A-D converter

8 bits ✕ 6 channels

D-A converter

8 bits ✕ 2 channels

DMAC

2 channels (trigger: 23 sources)

OSD function

Triple layer, 890 kinds of fonts, 42 characters ✕ 16 lines

Data slicer

Data slicer0

16-bit ✕ 2, or data buffer of 16-bit and 20-bit

Data slicer1

16-bit ✕ 2, or data buffer of 16-bit and 20-bit

HSYNC counter

8 bits ✕ 2 channels

Watchdog timer

15 bits ✕ 1 (with prescaler)

Interrupt

22 internal and 3 external sources, 4 software sources, 7 levels

Clock generating circuit

3 built-in clock generation circuits

Power source voltage

VCCE(5V system I/O power supply) 4.75 V to 5.25V

VCCI(internal logic power supply)

3.15 V to 3.45V

Power consumption

415mW

I/O

I/O withstand voltage

3.3 V (only P67, P70, P71, P72, P93 and P94 : 5V )

characteristics

Output current

5 mA

Memory expansion

Available

Operating ambient temperature

–20 o C to 70 o C

Device configuration

CMOS high performance silicon gate

Package

100-pin plastic molded QFP

Table 1.5.1 Performance outline

1.5 Performance Outline

Table 1.5.1 is a performance outline.

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