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6V7 Datasheet(PDF) 64 Page - Renesas Technology Corp

Part # 6V7
Description  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PDF  298 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

6V7 Datasheet(HTML) 64 Page - Renesas Technology Corp

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Rev.1.00
May 18, 2004
page 64 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.7.18 Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents
match the program counter value. Two address match interrupts can be set, each of which can be
enabled and disabled by an address match interrupt enable bit. Address match interrupts are not af-
fected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the
program counter (PC) for an address match interrupt varies depending on the instruction being executed.
Figures 2.7.12 and 2.7.13 show the address match interrupt-related registers.
Bit name
Bit symbol
Symbol
Address
When reset
AIER
000916
XXXXXX002
Address match interrupt enable register
Function
W
R
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
Symbol
Address
When reset
RMAD0
001216 to 001016
X0000016
RMAD1
001616 to 001416
X0000016
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
b7
b6
b5
b4
b3
b2
b1
b0
W
R
Address setting register for address match interrupt
Function
Values that can be set
Address match interrupt register i (i = 0, 1)
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7
b0
b3
(b19)
(b16)
b7
b0
(b15)
(b8)
b7
(b23)
Figure 2.7.13 Address match interrupt register i (i = 0, 1)
Figure 2.7.12 Address match interrupt enable register



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