STV0299B datasheet(17/36 Pages) STMICROELECTRONICS

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STV0299B

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FUNCTIONAL DESCRIPTION (continued)

4.6.8

Serial Output Interface

The serial output interface is shown in Figure 6.

The

serial

bit

stream

available

D7,

where MSB is first to reconstruct the original

order. If RS0 = 0, then the parity bits are output

(Register 33). If RS0 = 1, the data is null during

the parity time slots.

STR_OUT is only high during the first bit of each

packet, instead of during the first byte in parallel

mode.

ERROR has the same function as in parallel

mode.

CLK_OUT is the serial bit clock; it is derived from

either the master clock, M_CLK, (if SerClk = 0 in

Registers 02 and B3), or from the internal VCO

frequency divided by 6, (if SerClk = 1), by skipping

some pulses to accommodate the frequency

difference.

All of the outputs are synchronous of the same

master clock edge.

D0, STR_OUT, D/P and ERROR may be properly

sampled

externally

the

rising

edge

CLK_OUT, if RS1 = 0, or by the falling edge of

CLK_OUT

RS1 = 1.

This

clock

runs

continuously, even during parity data, whatever

the value of RS0.

The first bit detected in a valid packet may be

decoded if it is found on the appropriate edge of

CLK_OUT, where STR_OUT = 1, ERROR = 0,

D/P = 1. The following bits only require the

assertion of D/P (while D/P = 1,...).

Outputs D0 to D6 remain at low level in serial

mode.

Figure 6:

Serial Output Interface

Figure 7:

Parallel Output Interface

STR_OUT

ERROR

RS0 = 0

RS0 = 1

RS0 = 0

RS0 = 1

RS1 = 1

RS1 = 0

D/P

Data

Parity

Useful Data

1 Packet

First bit of the packet

1/f

M-CLK

CLK_OUT

or 6/f

VCO

Data

Parity

No Error

Uncorrectible Packet

No Error

CLK_OUT

D/P

STR_OUT

ERROR

RS1 = 0

RS1 = 1

RS0 = 0

RS0 = 1

RS0 = 0

RS0 = 1

RS0 = 0

RS0 = 1

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