M32C83T datasheet(80/527 Pages) RENESAS

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Page 57

7. Bus

)

(

7.2.3 Read and Write Signals

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When set to the 16-bit data bus, the PM02 bit in the PM0 register selects a combination of the RD, WR

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and BHE signals or the RD, WRL and WRH signals to determine the read or write signal. When the DS3

_____ ______ ________

to DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). If any

of the DS3 to DS0 bits are set to "1" (16-bit data bus) when accessing an 8-bit space, the combination of

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______

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RD, WR and BHE is automatically selected regardless of the PM02 bit setting. Tables 7.3 and 7.4 list

each signal operations.

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The RD, WR and BHE signals are combined for the read or write signal after reset.

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When changing the combination to RD, WRL and WRH, set the PM02 bit before writing data to an

external memory.

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When using the DRAMC to access the DRAM with the 16-bit bus, set the PM02 bit to "1" (RD/ WRL/

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WRH).

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Table 7.3 RD, WRL and WRH Signals

Status of External Data Bus

LHL

HLH

Write 1-byte data to odd address

Read 1-byte data from odd address

Write 1-byte data to even address

Read 1-byte data from even address

Data Bus

LHL

H / L

8 Bits

Write data to both even and odd addresses

Read data from both even and odd addresses

Write 1-byte data

Read 1-byte data

16 Bits

BHE

Not used

Status of External Data Bus

Read data

Write 1-byte data to even address

Write 1-byte data to odd address

Write data to both even and odd addresses

WRH

WRL

Data Bus

16 Bits

H(1)

L(1)

Not used

Write 1-byte data

Read 1-byte data

Not used

8 Bits

NOTES:

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1. The WR signal is used instead of the WRL signal.

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Table 7.4 RD, WR and BHE Signals

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