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M32C83T Datasheet(PDF) 96 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 96 Page - Renesas Technology Corp |
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96 / 527 page  Page 73 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 8. Clock Generation Circuit ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M PLC11 (b0) (b3) (b7 - b4) PLC12 Function PLL Control Register 1(1, 2) PLL Clock Division Enable Bit(3) Reserved Bit 0 : Disables the PLL clock to be divided 1 : Enables the PLL clock to be divided 0 : Divide-by-2 1 : Divide-by-3 Set to "0" PLL Clock Division Switch Bit(4) Bit Name Bit Symbol Symbol Address After Reset PLC1 037716 XXXX 00002 RW RW RW RW Reserved Bit Set to "0" RW NOTES: 1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. Rewrite the PLC1 register after the CM17 bit in the CM1 register is set to "0" (main clock) . 3. When the CM21 bit in the CM2 register is set to "0" (clock selected by the CM17 bit), if the PLC11 bit is set to "1" before the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock divided- by-2 or divided-by-3 becomes the clock source of the CPU clock and peripheral function clock. 4. Do not rewrite the PLC12 bit if the PLL clock is the CPU clock source. b7 b6 b5 b4 b3 b2 b1 b0 0 0 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Figure 8.8 PLC1 Register |
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