M32C83T datasheet(113/527 Pages) RENESAS

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10. Interrupts

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10.2.4 BRK2 Interrupt

The BRK2 interrupt occurs when the BRK2 instruction is executed.

Do not use this interrupt. For development support tools only.

10.2.5 INT Instruction Interrupt

The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select

software interrupt numbers 0 to 63. Software interrupt numbers 7 to 54, and 57 are assigned to the vector

table used for the peripheral function interrupt. Therefore, the microcomputer executes the same service

routine when the INT instruction is executed as when a peripheral function interrupt occurs.

When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the

relocatable vector of the specified software interrupt number. Where the stack is saved varies, depend-

ing on the software interrupt number. ISP is selected as the stack for the software interrupt numbers 0 to

31 (the U flag is set to "0"). SP, which is set before the INT instruction is executed, is selected as the stack

for the software interrupt numbers 32 to 63 (the U flag is not changed).

With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select)

when an interrupt request is acknowledged. With software interrupt numbers 32 to 54 and 57, the SP to

be used varies, depending on whether the interrupt is generated by the peripheral function interrupt

request or by the INT instruction.

10.3 Hardware Interrupts

Special interrupts and peripheral function interrupts are available as hardware interrupts.

10.3.1 Special Interrupts

Special interrupts are non-maskable interrupts.

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10.3.1.1 NMI Interrupt

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The NMI interrupt occurs when a signal applied to the NMI pin changes from an "H" signal to an "L"

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signal. Refer to 10.8 NMI Interrupt for details.

10.3.1.2 Watchdog Timer Interrupt

The watchdog timer interrupt occurs when the count source of the watchdog timer underflows. Refer

to 11. Watchdog Timer for details.

10.3.1.3 Oscillation Stop Detection Interrupt

The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscilla-

tion stop. Refer to 8. Clock Generating Circuit for details.

10.3.1.4 Single-Step Interrupt

Do not use the single-step interrupt. For development support tool only.

10.3.1.5 Address Match Interrupt

The address match interrupt occurs immediately before executing an instruction that is stored into an

address indicated by the RMADi register (i=0 to 3) when the AIERi bit in the AIER register is set to "1"

(address match interrupt enabled). Set the starting address of the instruction in the RMADi register.

The address match interrupt does not occur when a table data or addresses of the instruction other

than the starting address, if the instruction has multiple addresses, is set. Refer to 10.10 Address

Match Interrupt for details.

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