SH7261 datasheet(111/1348 Pages) RENESAS

111 / 1348 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 79 of 1312

REJ09B0320-0200

The clock pulse generator blocks function as follows:

(1)

PLL Circuit 1

PLL circuit 1 multiplies the input clock frequency from the CKIO pin by 1, 2, 3, 4, 6, or 8. The

multiplication rate is set by the frequency control register. When this is done, the phase of the

rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge

of the CKIO pin.

(2)

PLL Circuit 2

PLL circuit 2 multiplies the input clock frequency from the crystal oscillator or EXTAL pin by 2

or 4. The multiplication rate is fixed according to the clock operating mode. The clock operating

mode is specified by the MD_CLK1 and MD_CLK0 pins. For details on the clock operating

mode, see table 4.2.

Note that the settings of these pins cannot be changed during operation. If changed, the operation

of this LSI cannot be guaranteed.

(3)

Crystal Oscillator

The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the

XTAL pin or EXTAL pin. This can be used according to the clock operating mode.

(4)

Divider

Divider generates a clock signal at the operating frequency used by the internal or peripheral

clock. The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8, or 1/12 times the output frequency

of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division

ratio is set in the frequency control register (FRQCR).

(5)

Clock Frequency Control Circuit

The clock frequency control circuit controls the clock frequency using the MD_CLK1 and

MD_CLK0 pins and the frequency control register (FRQCR).

(6)

Standby Control Circuit

The standby control circuit controls the states of the clock pulse generator and other modules

during clock switching, or in sleep, software, and deep standby mode.

SH7261 Datasheet(PDF) 111 Page - Renesas Technology Corp