SH7261 datasheet(112/1348 Pages) RENESAS

112 / 1348 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 80 of 1312

REJ09B0320-0200

(7)

Frequency Control Register (FRQCR)

The frequency control register (FRQCR) has control bits assigned for the following functions:

clock output/non-output from the CKIO pin during software standby mode, the frequency

multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the

peripheral clock (P

φ).

(8)

Standby Control Register

The standby control register has bits for controlling the power-down modes. See section 27,

Power-Down Modes, for more information.

4.2

Input/Output Pins

Table 4.1 lists the clock pulse generator pins and their functions.

Table 4.1

Pin Configuration and Functions of the Clock Pulse Generator

Pin Name

Symbol

I/O

Function

(Clock Operating

Modes 0 and 2)

Function

(Clock Operating

Mode 3)

MD_CLK0

Input

Sets the clock operating

mode.

Sets the clock operating

mode.

Mode control pins

MD_CLK1

Input

Sets the clock operating

mode.

Sets the clock operating

mode.

XTAL

Output

Connected to the crystal

resonator. (Leave this pin

open when the crystal

resonator is not in use.)

Leave this pin open.

Crystal

input/output pins

(clock input pins)

EXTAL

Input

Connected to the crystal

resonator or used to input

an external clock.

Pull-up this pin.

Clock input/output

CKIO

I/O

Clock output pin.

Clock input pin.

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