HD6417618 datasheet(251/646 Pages) RENESAS

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Section 10 Power-Down Modes

Rev. 6.00 Jun. 12, 2007 Page 219 of 610

REJ09B0131-0600

10.3.2

Standby Control Register 2 (STBCR2)

STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-

down mode.

Bit

Bit Name

Initial

Value

R/W

Description

MSTP10

R/W

Module Stop Bit 10

When this bit is set to 1, the supply of the clock to

the H-UDI is halted.

0: H-UDI operates

1: Clock supply to H-UDI halted

MSTP9

R/W

Module Stop Bit 9

When this bit is set to 1, the supply of the clock to

the UBC is halted.

0: UBC operates

1: Clock supply to UBC halted

5 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

MSTP5

R/W

Module Stop Bit 5

When this bit is set to 1, the supply of the clock to

the cache memory is halted.

0: Cache memory operates

1: Clock supply to cache memory halted

MSTP4

R/W

Module Stop Bit 4

When this bit is set to 1, the supply of the clock to

the U memory is halted.

0: U memory operates

1: Clock supply to the U memory halted



Reserved

This bit is always read as 0. The write value should

always be 0.

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