HD6432351 datasheet(895/1025 Pages) RENESAS

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Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 861 of 988

REJ09B0330-0300

DMABCRH—DMA Band Control Register

H'FF06

DMAC

DMABCRL—DMA Band Control Register

H'FF07

DMAC

FAE1

R/W

FAE0

R/W

—

R/W

—

R/W

DTA1

R/W

—

R/W

—

R/W

DTA0

R/W

Full address mode

Bit

DMABCRH

Initial value

Read/Write

Short address mode

Full address mode

Channel 1 Full Address Enable

Short address mode

Full address mode

Channel 0 Full Address Enable

Clearing of selected internal interrupt source at time of

DMA transfer is disabled

Channel 1 Data Transfer Acknowledge

Clearing of selected internal interrupt source at time of

DMA transfer is enabled

Clearing of selected internal interrupt source at time of

DMA transfer is disabled

Channel 0 Data Transfer Acknowledge

Clearing of selected internal interrupt source at time of

DMA transfer is enabled

(Continued on next page)

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