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HD6432351 Datasheet(PDF) 892 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 892 Page - Renesas Technology Corp |
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892 / 1025 page  Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 858 of 988 REJ09B0330-0300 DMACR0A—DMA Control Register 0A H'FF02 DMAC DMACR0B—DMA Control Register 0B H'FF03 DMAC DMACR1A—DMA Control Register 1A H'FF04 DMAC DMACR1B—DMA Control Register 1B H'FF05 DMAC 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 8 — 0 R/W 10 — 0 R/W 9 — 0 R/W 0 1 Byte-size transfer Word-size transfer Data Transfer Size 0 1 Source Address Increment/Decrement 0 1 0 1 MARA is fixed MARA is incremented after a data transfer MARA is fixed MARA is decremented after a data transfer 0 1 Block Direction/Block Enable 0 1 0 1 Transfer in normal mode Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area Full address mode Bit DMACRA Initial value Read/Write : : : : |
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