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HD6432351 Datasheet(PDF) 891 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 891 Page - Renesas Technology Corp |
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891 / 1025 page ![]() Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 857 of 988 REJ09B0330-0300 DMATCR—DMA Terminal Control Register H'FF01 DMAC 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W 3 — 0 — 0 — 0 — 2 — 0 — 1 — 0 — Bit DMATCR Initial value Read/Write : : : : Transfer End Enable 1 0 1 Transfer End Enable 0 0 1 TEND0 pin output disabled TEND0 pin output enabled TEND1 pin output disabled TEND1 pin output enabled |
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