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HD6432351 Datasheet(PDF) 894 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 894 Page - Renesas Technology Corp |
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894 / 1025 page  Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 860 of 988 REJ09B0330-0300 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 0 DTF0 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W Short address mode Bit DMACR Initial value Read/Write : : : : 0 — Data Transfer Factor 0 0 0 Channel A Channel B Activated by TPU channel 5 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by SCI channel 1 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 0 transmission complete interrupt — Activated by A/D converter conversion end interrupt 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 10 1 1 10 1 — — Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe 0 1 Byte-size transfer Word-size transfer Data Transfer Size 0 1 MAR is incremented after a data transfer MAR is decremented after a data transfer Data Transfer Increment/Decrement 0 1 Transfer in sequential mode Transfer in repeat mode or idle mode Repeat Enable 0 1 Data Transfer Direction Dual address mode: Transfer with IOAR as source address and MAR as destination address Single address mode: Transfer with DACK pin as read strobe and MAR as destination address Activated by DREQ pin falling edge input Activated by DREQ pin low-level input — |
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