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HD6432351 Datasheet(PDF) 893 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 893 Page - Renesas Technology Corp |
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893 / 1025 page  Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 859 of 988 REJ09B0330-0300 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 0 DTF0 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 1 Destination Address Increment/Decrement 0 1 0 1 MARB is fixed MARB is incremented after a data transfer MARB is fixed MARB is decremented after a data transfer — — — — — Auto-request (burst) — — — — — — — — Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt 0 1 Data Transfer Factor 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Block Transfer Mode DTF 3 DTF 2 DTF 1 DTF 0 Normal Mode — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Full address mode (cont) Bit DMACRB Initial value Read/Write : : : : Auto-request (cycle steal) |
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