HD6432351 datasheet(262/1025 Pages) RENESAS

262 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 228 of 988

REJ09B0330-0300

7.4

7.4.1

DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the

transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions

so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can

be changed to prevent inadvertent rewriting of registers other than those for the channel

concerned. The restrictions applied by DMAWER are valid for the DTC.

Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end

interrupt, and reactivating channel 0A. The address register and count register area is re-set by the

first DTC transfer, then the control register area is re-set by the second DTC chain transfer.

When re-setting the control register area, perform masking by setting bits in DMAWER to prevent

modification of the contents of the other channels.

DTC

MAR0A

IOAR0A

ETCR0A

MAR0B

IOAR0B

ETCR0B

MAR1A

IOAR1A

ETCR1A

MAR1B

IOAR1B

ETCR1B

DMATCR

DMACR0B

DMACR1B

DMAWER

DMACR0A

DMACR1A

DMABCR

Second transfer area

using chain transfer

First transfer area

Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)

HD6432351 Datasheet(PDF) 262 Page - Renesas Technology Corp