HD6432351 datasheet(265/1025 Pages) RENESAS

265 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 231 of 988

REJ09B0330-0300

7.4.2

DMA Terminal Control Register (DMATCR)

—

TEE1

R/W

TEE0

R/W

—

Bit

DMATCR

Initial value

R/W

DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC

transfer end pin output. A port can be set for output automatically, and a transfer end signal output,

by setting the appropriate bit.

DMATCR is initialized to H'00 by a reset, and in standby mode.

Bits 7 and 6—Reserved: Read-only bits, always read as 0.

Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (

TEND1) output.

Bit 5

TEE1

Description

TEND1 pin output disabled

(Initial value)

TEND1 pin output enabled

Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (

TEND0) output.

Bit 4

TEE0

Description

TEND0 pin output disabled

(Initial value)

TEND0 pin output enabled

The

TEND pins are assigned only to channel B in short address mode.

The transfer end signal indicates the transfer cycle in which the transfer counter reached 0,

regardless of the transfer source. An exception is block transfer mode, in which the transfer end

signal indicates the transfer cycle in which the block counter reached 0.

Bits 3 to 0—Reserved: Read-only bits, always read as 0.

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