HD6432351 datasheet(263/1025 Pages) RENESAS

263 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 229 of 988

REJ09B0330-0300

—

WE1B

R/W

WE0A

R/W

WE1A

R/W

WE0B

R/W

Bit

DMAWER

Initial value

R/W

DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the

DMACR, DMABCR, and DMATCR by the DTC.

DMAWER is initialized to H'00 by a reset, and in standby mode.

Bits 7 to 4—Reserved: Read-only bits, always read as 0.

Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7,

and 3 in DMABCR, and bit 5 in DMATCR by the DTC.

Bit 3

WE1B

Description

Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

are disabled

(Initial value)

Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

are enabled

Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits

10, 6, and 2 in DMABCR by the DTC.

Bit 2

WE1A

Description

Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled

(Initial value)

Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled

Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,

and 1 in DMABCR, and bit 4 in DMATCR.

Bit 1

WE0B

Description

Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

are disabled

(Initial value)

Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

are enabled

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