HD6432147SW datasheet(408/1177 Pages) RENESAS

Part #	HD6432147SW

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1177 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 8-Bit Timers

Rev. 4.00 Sep 27, 2006 page 364 of 1130

REJ09B0327-0400

Timer Output Timing

When compare-match A or B occurs, the timer output changes as specified by the output select

bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0,

be set to 1, or toggle.

Figure 12.5 shows the timing when the output is set to toggle at compare-match A.

Compare-match A

signal

Timer output

Figure 12.5 Timing of Timer Output

Timing of Compare-Match Clear

TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and

CCLR0 bits in TCR. Figure 12.6 shows the timing of this operation.

H'00

Compare-match

signal

TCNT

Figure 12.6 Timing of Compare-Match Clear

12.3.3

TCNT External Reset Timing

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the

CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure

12.7 shows the timing of this operation.

HD6432147SW Datasheet(PDF) 408 Page - Renesas Technology Corp