HD6432147SW datasheet(22/1177 Pages) RENESAS

22 / 1177 page

Rev. 4.00 Sep 27, 2006 page xxii of xliv

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Page

Revision (See Manual for Details)

B.3 Functions

1013

Subheading amended

KBCOMP

H'FEE4 IrDA/Expansion A/D

1016

ISR

H'FEEB Interrupt Controller

Figure amended

IRQ7 to IRQ0 flags

[Clearing conditions]

• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF

• When interrupt exception handling is executed while low-level detection

is set (IRQnSCB = IRQnSCA = 0) and

IRQn input is high*

• When IRQn interrupt exception handling is executed while falling, rising,

or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)*

Note: * When a product, in which a DTC is incorporated, is

used in the following settings, the corresponding flag bit is not

automatically cleared even when exception handling, which is a

clear condition, is executed and the bit is held at 1.

(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source),

IRQ4F flag is not automatically cleared.

(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt

source), IRQ5F flag is not automatically cleared.

(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt

source), IRQ6F flag is not automatically cleared.

(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt

source), IRQ7F flag is not automatically cleared.

When activation interrupt sources of DTC and IRQ interrupts

are used with the above combinations, clear the interrupt flag

by software in the interrupt handling routine of the

corresponding IRQ.

1019

ABRKCR

H'FEF4 Interrupt Controller

Read/Write description amended

Bit 7 (Before) R/W

→ (After) R

1021

FLMCR1

H'FF80 Flash Memory

Initial value description amended

Bit 7 (Before)

 → (After) 1

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