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HD6432147SW Datasheet(PDF) 15 Page - Renesas Technology Corp |
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HD6432147SW Datasheet(HTML) 15 Page - Renesas Technology Corp |
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15 / 1177 page  Rev. 4.00 Sep 27, 2006 page xv of xliv Item Page Revision (See Manual for Details) 23.6.1 Boot Mode 705 Description amended H'(FF)E088 and above 23.7.2 Program-Verify Mode Figure 23.12 Program/Program-Verify Flowcharts 710 Note *6 added to figure 23.12 Start End of programming End sub Set SWE bit in FLMCR1 Wait (x) µs n = 1 m = 0 Sub-routine-call See Note 7 for pulse width Note 7: Write Pulse Width Start of programming Sub-routine write pulse Set PSU bit in FLMCR1 Enable WDT Set P bit in FLMCR1 Wait (y) µs Clear P bit in FLMCR1 Wait (z1) µs, (z2) µs or (z3) µs Clear PSU bit in FLMCR2 Wait ( α) µs Disable WDT Wait ( β) µs Write pulse application subroutine NG NG NG NG OK OK Wait ( γ) µs Wait ( ε) µs *2 *4 *6 *6 *6 *6 *6 *6 *6 *6 *5 *6 *6 *6 *1 Wait ( η) µs Set PV bit in FLMCR1 H'FF dummy write to verify address Read verify data Program data = verify data? Transfer additional program data to additional program data area Additional program data computation Clear PV bit in FLMCR1 Clear SWE bit in FLMCR1 m = 1 End of 128-byte data verification? m = 0? Increment address Programming failure OK Write 128-byte data in RAM reprogram data area consecutively to flash memory Write pulse (z1) µs or (z2) µs RAM Program data storage area (128 bytes) Reprogram data storage area (128 bytes) Store 128-byte program data in program data area and reprogram data area Number of Writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 ... 998 999 1000 Write Time (z*6) µsec z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 ... z2 z2 z2 Reprogram data computation Transfer reprogram data to reprogram data area *4 *3 6 ≥ n? NG OK Write 128-byte data in additional program data area in RAM consecutively to flash memory Additional write pulse (z3) µs Wait ( θ) µs *1 Note: Use a (z3) µs write pulse for additional programming. Additional program data storage area (128 kbytes) OK OK NG Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *4 n ← n + 1 n ≥ 1000? Clear SWE bit in FLMCR1 Wait ( θ) µs 6 ≥ n? 23.10.4 Memory Read Mode Figure 23.17 Timing Waveforms when Entering Another Mode from Memory Read Mode 721 Figure 23.17 amended CE FA17 to FA0 FO7 to FO0 H'XX OE WE Other mode command write twep tceh tdh tds tces Data tf tr Memory read mode Address stable tnxtc |
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