HD6432147SW datasheet(23/1177 Pages) RENESAS

23 / 1177 page

Rev. 4.00 Sep 27, 2006 page xxiii of xliv

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Page

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B.3 Functions

1025

EBR1

H'FF82 Flash Memory

EBR2

H'FF83 Flash Memory

Figure amended

Read/Write description of bits 7 to 2 (Before)

*2 → (After) 

—

EB8/—*2

R/W*1*2

—

EB9/—*2

R/W*1*2

Bit

EBR1

Initial value

Read/Write

EB7

R/W*1

EB6

R/W

EB5

R/W

EB4

R/W

EB3

R/W

EB0

R/W

EB2

R/W

EB1

R/W

Bit

EBR2

Initial value

Read/Write

1030

ICCR1

H'FF88 IIC1

ICCR0

H'FFD8 IIC0

Figure amended

I2C bus interface enable

I2C bus interface module disabled, with

SCL and SDA signal pins set to port

function

SAR and SARX can be accessed

1I2C bus interface module enabled for

transfer operations (pins SCL and SDA

are driving the bus)

ICMR and ICDR can be accessed

1059

SYSCR

H'FFC4 System

Figure amended

IOS enable

Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version,

the address range is from H'(FF)F000 to H'(FF)F7FF.

The

AS/IOS pin functions as the address strobe pin

(Low output when accessing an external area)

The

AS/IOS pin functions as the I/O strobe pin

(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)*

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