HD6432147SW datasheet(171/1177 Pages) RENESAS

171 / 1177 page

Section 5 Interrupt Controller

Rev. 4.00 Sep 27, 2006 page 127 of 1130

REJ09B0327-0400

IRQn interrupt

request

IRQnE

IRQnF

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input

Note: n: 7 to 0

Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0

Figure 5.4 shows the timing of IRQnF setting.

IRQn

input pin

IRQnF

Figure 5.4 Timing of IRQnF Setting

The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.

Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for

input or output. Therefore, when a pin is used as an external interrupt input pin, clear the

corresponding DDR bit to 0 and do not use the pin as an I/O pin for another function. When the

IRQ6 pin is assigned as the IRQ6 interrupt input pin, then set the KMIMR6 bit to 0.

When the

IRQ7 pin is used as the IRQ7 interrupt input pin, bits KMIMR15 to KMIMR8 must all

be set to 1. If any of these bits is cleared to 0, interrupt input from the

IRQ7 pin will be ignored.

As interrupt request flags IRQ7F to IRQ0F are set when the setting condition is met, regardless of

the IER setting, only the necessary flags should be referenced.

HD6432147SW Datasheet(PDF) 171 Page - Renesas Technology Corp