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HD6432147SW Datasheet(PDF) 244 Page - Renesas Technology Corp |
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HD6432147SW Datasheet(HTML) 244 Page - Renesas Technology Corp |
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244 / 1177 page  Section 7 Data Transfer Controller (DTC) Rev. 4.00 Sep 27, 2006 page 200 of 1130 REJ09B0327-0400 7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.9 shows memory mapping for chain transfer. Source Source Destination Destination DTC vector address Register information start address Register information CHNE = 1 Register information CHNE = 0 Figure 7.9 Memory Mapping in Chain Transfer In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. |
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