HD6432142 datasheet(371/1177 Pages) RENESAS

Part #	HD6432142

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1177 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 11 16-Bit Free-Running Timer

Rev. 4.00 Sep 27, 2006 page 327 of 1130

REJ09B0327-0400

11.3.3

FRC Clear Timing

FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this

operation.

H'0000

FRC

Compare-match A

signal

Figure 11.6 Clearing of FRC by Compare-Match A

11.3.4

Input Capture Input Timing

An internal input capture signal is generated from the rising or falling edge of the signal at the

input capture pin, as selected by the corresponding IEDGx (x = A to D) bit in TCR. Figure 11.7

shows the usual input capture timing when the rising edge is selected (IEDGx = 1).

Input capture

signal

Input capture

input pin

Figure 11.7 Input Capture Signal Timing (Usual Case)

If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal

arrives, the internal input capture signal is delayed by one system clock (

φ) period. Figure 11.8

shows the timing for this case.

HD6432142 Datasheet(PDF) 371 Page - Renesas Technology Corp