HD6432142 datasheet(373/1177 Pages) RENESAS

373 / 1177 page

Section 11 16-Bit Free-Running Timer

Rev. 4.00 Sep 27, 2006 page 329 of 1130

REJ09B0327-0400

When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected

transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge

transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and

if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to

ICRC, however.

In buffered input capture, if the upper byte of either of the two registers to which data will be

transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives,

input capture is delayed by one system clock (

φ) period. Figure 11.10 shows the timing when

BUFEA = 1.

Input capture

signal

FTIA

Read cycle:

CPU reads ICRA or ICRC

Figure 11.10 Buffered Input Capture Timing

(Input Capture Input when ICRA or ICRC Is Read)

11.3.5

Timing of Input Capture Flag (ICF) Setting

The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. The

FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure

11.11 shows the timing of this operation.

HD6432142 Datasheet(PDF) 373 Page - Renesas Technology Corp