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HD6432142 Datasheet(PDF) 374 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 374 Page - Renesas Technology Corp |
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374 / 1177 page  Section 11 16-Bit Free-Running Timer Rev. 4.00 Sep 27, 2006 page 330 of 1130 REJ09B0327-0400 ICFA/B/C/D φ FRC Input capture signal N N ICRA/B/C/D Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D) 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA and OCFB. OCRA or OCRB φ Compare-match signal FRC N N + 1 N OCFA or OCFB Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB) |
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