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HD6432142 Datasheet(PDF) 464 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 464 Page - Renesas Technology Corp |
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464 / 1177 page ![]() Section 14 Watchdog Timer (WDT) Rev. 4.00 Sep 27, 2006 page 420 of 1130 REJ09B0327-0400 14.5 Usage Notes 14.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T 2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.7 shows this operation. Address φ Internal write signal TCNT input clock TCNT NM T1 T2 TCNT write cycle Counter write data Figure 14.7 Contention between TCNT Write and Increment 14.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. |
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