HD6432142 datasheet(647/1177 Pages) RENESAS

647 / 1177 page

Section 18 Host Interface

Rev. 4.00 Sep 27, 2006 page 603 of 1130

REJ09B0327-0400

HIRQ Setting/Clearing Contention

If there is contention between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11,

HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held

pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is

executed after completion of the read/write.

18.5

Usage Note

The following points require attention when using the host interface.

(1) Host and slave transmission/reception procedures

The host interface provides buffering of asynchronous data from the host and slave processors,

but an interface protocol must be followed to implement necessary functions and avoid data

contention. For example, if the host and slave processors try to access the same input or output

data register simultaneously, the data will be corrupted. Interrupts can be used to design a

simple and effective protocol.

(2) Preventing data contention on the HDB

When the HIF function is used (HI12E = 1 in SYSCR2) and channel 3 or channel 4 has been

set as deselected (CS3E = 0 or CS4E = 0 in SYSCR2), apply either of the following usage

conditions.

1. Ensure that the

CS pin for the deselected channel is fixed high.

2. Do not perform port B reads.

(3) Preventing through-current in pins

CS1 to CS4

Also, if two or more of pins

CS1 to CS4 are driven low simultaneously in attempting IDR or

ODR access, signal contention will occur within the chip, and a through-current may result.

This usage must therefore be avoided.

HD6432142 Datasheet(PDF) 647 Page - Renesas Technology Corp