HD6432142 datasheet(646/1177 Pages) RENESAS

646 / 1177 page

Section 18 Host Interface

Rev. 4.00 Sep 27, 2006 page 602 of 1130

REJ09B0327-0400

Table 18.10 HIRQ Setting/Clearing Conditions

Host Interrupt

Signal

Setting Condition

Clearing Condition

HIRQ11

(P43)

Internal CPU reads 0 from bit P43DR,

then writes 1

Internal CPU writes 0 in bit P43DR, or

host reads output data register 2

HIRQ1

(P44)

Internal CPU reads 0 from bit P44DR,

then writes 1

Internal CPU writes 0 in bit P44DR, or

host reads output data register 1

HIRQ12

(P45)

Internal CPU reads 0 from bit P45DR,

then writes 1

Internal CPU writes 0 in bit P45DR, or

host reads output data register 1

HIRQ3

(PB0)

Internal CPU reads 0 from bit PB0ODR,

then writes 1

Internal CPU writes 0 in bit PB0ODR,

or host reads output data register 3

HIRQ4

(PB1)

Internal CPU reads 0 from bit PB1ODR,

then writes 1

Internal CPU writes 0 in bit PB1ODR,

or host reads output data register 4

Slave CPU

Master CPU

Write to ODR

Write 1 to P4DR

P4DR = 0?

Yes

All bytes

transferred?

HIRQ output high

HIRQ output low

Interrupt initiation

ODR read

Hardware operations

Software operations

Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2)

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