HD6432142 datasheet(643/1177 Pages) RENESAS

643 / 1177 page

Section 18 Host Interface

Rev. 4.00 Sep 27, 2006 page 599 of 1130

REJ09B0327-0400

Table 18.7

Fast A20 Gate Output Signal

HA0

Data/Command

Internal CPU

Interrupt Flag

GA20

(P81)

Remarks

H'D1 command

1 data*

H'FF command

Q (1)

Turn-on sequence

H'D1 command

0 data*

H'FF command

Q (0)

Turn-off sequence

1/0

H'D1 command

1 data*

Command other than H'FF

and H'D1

Q (1)

Turn-on sequence

(abbreviated form)

1/0

H'D1 command

0 data*

Command other than H'FF

and H'D1

Q (0)

Turn-off sequence

(abbreviated form)

H'D1 command

Command other than H'D1

Cancelled sequence

H'D1 command

Retriggered sequence

H'D1 command

Any data

H'D1 command

1/0

Q(1/0)

Consecutively executed

sequences

Notes: 1. Arbitrary data with bit 1 set to 1.

2. Arbitrary data with bit 1 cleared to 0.

18.3.4

Host Interface Pin Shutdown Function

Host interface output can be placed in the high-impedance state according to the state of the

HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register enables the HIFSD pin is slave mode.

The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface

output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the high-impedance state.

At the same time, the host interface input pins (

CS1, CS2 or ECS2, CS3, CS4, IOW, IOR, and

HA0) are disabled (fixed at the high input state internally) regardless of the pin states, and the

signals of the multiplexed functions of these pins (input block) are similarly fixed internally. As a

result, the host interface I/O pins (HDB7 to HDB0) also go to the high-impedance state.

This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the high-

level state, the pins are restored to their normal operation as host interface pins.

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