HD6432142 datasheet(639/1177 Pages) RENESAS

639 / 1177 page

Section 18 Host Interface

Rev. 4.00 Sep 27, 2006 page 595 of 1130

REJ09B0327-0400

18.2.7

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.

When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section

25.5, Module Stop Mode, for details.

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface module stop mode.

MSTPCRL

Bit 2

MSTP2

Description

Host interface module stop mode is cleared

Host interface module stop mode is set

(Initial value)

18.3

Operation

18.3.1

Host Interface Activation

The HIF (slave mode) is activated by setting the HI12E bit (bit 0) in SYSCR2 to 1 in single-chip

mode. When the HIF (slave mode) is activated, all related I/O ports (data port 3, control ports 8

and 9, and host interrupt request port 4) become dedicated host interface ports. Setting the CS3E

bit and CS4E bit to 1 enables the number of HIF channels to be extended to a four, and makes the

channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated

host interface port.

Table 18.4 shows HIF host interface channel selection and pin operation.

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